This invention relates generally to charge-coupled devices (CCDs), and more particularly relates to the design and fabrication of CCD gate electrodes.
Conventionally, overlapping gate electrode configurations are employed for CCD designs, with timing control for CCD charge collection and transfer imposed on a charge transfer channel by the gate electrodes. In an overlapping gate electrode configuration, two or more layers of electrically conducting gate electrode material are deposited and patterned to define adjacent gate electrodes, the edges of which overlap along the length of the charge transfer channel. The effective gap width between such overlapping gate electrodes is on the order of the thickness of the dielectric layer that isolates the electrode overlap, which is on the scale of angstroms. This narrow effective gap width enables a high charge transfer efficiency from one gate electrode to the next by substantially inhibiting formation of electrical potential barriers in the charge transfer channel between adjacent gate electrodes.
Although this overlapping CCD gate electrode design does indeed enable a high charge transfer efficiency, it introduces significant complexity into a CCD microfabrication process. For example, the thermal processing required for each separate gate electrode layer subjects the various device regions to increased heat cycling, which the device design must take into account. Further, the lithographic and etching steps required for multiple gate electrode layers increases the probability of process errors and defects that reduce the overall yield of the device fabrication sequence. As imaging applications continue to demand larger arrays of CCD elements and smaller elements within an array, process errors, fabrication defects, and reduced fabrication yield become increasing limitations, and process cost and time become increasingly burdensome.
A single-level-gate CCD design has been shown to reduce the microfabrication complexity associated with multi-layer, overlapping gate electrode designs. In addition, a single-level-gate CCD design is known to reduce the thermal budget of a CCD microfabrication sequence and can reduce the number of required processing steps. In terms of device operation, the elimination of overlapping gate electrodes can reduce CCD gate capacitance and therefore can reduce the power required to drive gate electrode control voltages.
Successful implementation of a single-level-gate CCD design requires that the interelectrode gap, i.e., the gap between adjacent gate electrodes, be quite small, e.g., on the order of 0.3 μm or less. This small interelectrode gap is needed so that a high charge transfer efficiency can be maintained with only moderate gate electrode control voltages, and is a requirement for most current CCD imaging applications. But the implementation of a single-level gate design having a small interelectrode gap width can be extremely challenging; it is found that fabrication defects can be increased and process yield decreased by various process steps added in an effort to reduce gap width. This is particularly the case for CCD fabrication sequences directed to applications that additionally require a large-area CCD array and/or small CCD element dimensions.